A demand exists for an integrated circuit that can achieve submicron resolution with sufficient line width control on a substrate. The surfaces of these integrated circuits must be patterned with extreme accuracy at submicron levels. Unfortunately, problems of surface contamination have occurred using prior methods of filling submicron trenches of vias and contacts in integrated circuits.
To meet this problem, several techniques have been developed which concentrate on the selective deposition of metal, such as tungsten, within the trenches of the vias and contact. Unfortunately, the selective deposition processes of tungsten and other contacting metals have resulted in contamination of the insulator surfaces of the integrated circuit workpiece. When depositing contacting metals selectively in trenches of vias and contacts, metal particulates have a tendency to deposit on other areas of the integrated circuit workpiece which result in electrical shorting of the circuitry. Consequently, when reducing the size of the vias and contacts in order to accommodate decreasing design rules to increase the speed of the integrated circuit, there is an offset disadvantage of an increase in sensitivity to metal contaminants which tend to cause damage and eventually short circuit the integrated circuit.
Therefore, a need has arisen for a simple method of filling trenches of vias and contacts in integrated circuits with a metal which will eliminate problems of contamination on the integrated circuit workpiece which can cause short circuiting of the entire integrated circuit.